Instruction Cycle

A program residing in the memory unit of the computer consists of a sequence of instructions. The program is executed by the computer through a cycle for each instruction. Each instruction cycle is subdivided into a sequence of subcycles or phases. In the basic computer, each instruction cycle consists of the following phases:

1. Fetch an instruction from memory.
2. Decode the instruction.
3. Read $T$. Upon the completion of step 4, the control returns to step 1 to fetch, decode, and execute the next instruction. This process continues indefinitely unless a HALT instruction is encountered.

Fetch and Decode

Initially, the program counter (PC) is loaded with the address of the first instruction in the program. The sequence counter (SC) is cleared to 0, providing a decoded timing signal $T_0$. After each clock pulse, SC is incremented by one, so that the timing signals go through a sequence $T_0$, $T_1$, $T_2$, and so on. The micro-operations for the fetch and decode phases can be specified by the following register transfer statements:

$T0: AR \leftarrow PC$

$T1: IR \leftarrow M[AR], PC \leftarrow PC + 1$

$T2: D0,...,D7 \leftarrow Decode IR(12-14), AR \leftarrow IR(0-11), I \leftarrow IR(15)$

Since only the address register (AR) is connected to the address inputs of memory, it is necessary to transfer the address from PC to AR during the clock transition associated with timing signal $T_0$. The instruction read from memory is then placed in the instruction register (IR) with the clock transition associated with timing signal $T_1$. At the same time, PC is incremented by one to prepare it for the address of the next instruction in the program. At time $T_2$, the operation code in IR is decoded, the indirect bit is transferred to flip-flop I, and the address part of the instruction is transferred to AR. Note that SC is incremented after each clock pulse to produce the sequence $T_0$, $T_1$, and $T_2$.

To provide the data path for the transfer of PC to AR, we must apply timing signal $T_0$ to achieve the following connection:

1. Place the content of PC onto the bus by making the bus selection inputs $S2S1S0$ equal to 010.
2. Transfer the content of the bus to AR by enabling the LD input of AR.

The next clock transition initiates the transfer from PC to AR since $T_0 = 1$. In timing signal $T_1$, it is necessary to use the following connections in the bus system:

1. Enable the read input of memory.
2. Place the content of memory onto the bus by making $S2S1S0 = 111$.
3. Transfer the content of the bus to IR by enabling the LD input of IR.
4. Increment PC by enabling the INR input of PC.

The next clock transition initiates the read and increment operations since $T_1 = 1$.

Determine the Type of Instruction

The timing signal that is active after the decoding is $T_3$. During time $T_3$, the control unit determines the type of instruction that was just read from memory. The three possible instruction types available in the basic computer are:

• Memory-reference instruction
• Register-reference instruction
• Input-output instruction

The decoder output $D_7$ is equal to 1 if the operation code is equal to binary 111. If $D_7 = 1$, the instruction is either a register-reference or input-output type. If $D_7 = 0$, the operation code specifies a memory-reference instruction. Control then inspects the value of the first bit of the instruction, which is now available in flip-flop I. If $D_7 = 0$ and $I = 1$, the instruction is a memory-reference instruction with an indirect address. It is then necessary to read the effective address from memory. The micro-operation for the indirect address condition can be symbolized by the register transfer statement: $AR \leftarrow M[AR]$

Initially, AR holds the address part of the instruction. This address is used during the memory read operation. The word at the address given by AR is read from memory and placed on the common bus. The LD input of AR is then enabled to receive the indirect address that resided in the 12 least significant bits of the memory word.

The three instruction types are subdivided into four separate paths. The selected operation is activated with the clock transition associated with timing signal $T_3$. This can be symbolized as follows:

$D7I'T3$: Execute a register-reference instruction

$D7I'T3$: Execute an input-output instruction

$D7I'T3$: $AR \leftarrow M[AR]$

When a memory-reference instruction with $I = 0$ is encountered, it is not necessary to do anything since the effective address is already in AR. However, the sequence counter SC must be incremented when $D_7T_3 = 1$, so that the execution of the memory-reference instruction can be continued with timing variable $T_4$. A register-reference or input-output instruction can be executed with the clock associated with timing signal $T_3$. After the instruction is executed, SC is cleared to 0, and control returns to the fetch phase with $T_0 = 1$.

Note that the sequence counter SC is either incremented or cleared to 0 with every positive clock transition. We adopt the convention that if SC is incremented, we will not write the statement $SC \leftarrow SC + 1$, but it will be implied that the control goes to the next timing signal in sequence. When SC is to be cleared, we will include the statement $SC \leftarrow 0$.

Register-Reference Instructions

Register-reference instructions are recognized by the control when $D_7 = 1$ and $I = 0$. These instructions use bits 0 through 11 of the instruction code to specify one of 12 instructions. These 12 bits are available in $IR(0-11)$. They were also transferred to AR during time $T_2$.

The control functions and micro-operations for the register-reference instructions are listed below. These instructions are executed with the clock transition associated with timing variable $T_3$. Each control function needs the Boolean relation $D_7I'T_3$, which we designate for convenience by the symbol $r$. The control function is distinguished by one of the bits in $IR(0-11)$. By assigning the symbol $B_i$ to bit $i$ of IR, all control functions can be simply denoted by $rB_i$. For example, the instruction CLA has the hexadecimal code 7800, which gives the binary equivalent 0111 1000 0000 0000. The first bit is a zero and is equivalent to $I'$. The next three bits constitute the operation code and are recognized from decoder output $D_7$. Bit 11 in IR is 1 and is recognized from $B_{11}$. The control function that initiates the micro-operation for this instruction is $D_7I'T_3B_{11} = rB_{11}$. The execution of a register-reference instruction is completed at time $T_3$. The sequence counter SC is cleared to 0, and the control goes back to fetch the next instruction with timing signal $T_0$.

The first seven register-reference instructions perform clear, complement, circular shift, and increment micro-operations on the AC or E registers. The next four instructions cause a skip of the next instruction in sequence when a stated condition is satisfied. The skipping of the instruction is achieved by incrementing PC once again (in addition to it being incremented during the fetch phase at time $T_1$). The condition control statements must be recognized as part of the control conditions. The AC is positive when the sign bit in $AC(15) = 0$; it is negative when $AC(15) = 1$. The content of AC is zero ($AC = 0$) if all the flip-flops of the register are zero. The HLT instruction clears a start-stop flip-flop S and stops the sequence counter from counting. To restore the operation of the computer, the start-stop flip-flop must be set manually.