const

Registers

A register is a group of flip-flops where each flip-flop can store one bit of information. An n-bit register has a group of n flip-flops, allowing it to store any binary information of n bits. Registers may also include combinational gates to perform data-processing tasks. Broadly defined, a register consists of a group of flip-flops and gates that control the transitions of these flip-flops. The flip-flops hold the binary information, and the gates manage when and how new information is transferred into the register.

Basic Register

The simplest register consists solely of flip-flops without any external gates. In a 4-bit register, four D flip-flops are commonly used. The flip-flops are triggered by a common clock input on the rising edge of each pulse, transferring the binary data available at the four inputs into the register. The outputs can be sampled at any time to obtain the stored binary information. The clear input, which is connected to a special terminal in each flip-flop, resets all flip-flops asynchronously when set to 0. This is useful for clearing the register before its clocked operation. The clear input must be maintained at logic 1 during normal operation. Note that the clock signal enables the D input, but the clear input operates independently of the clock.

Parallel Loading of Registers

The transfer of new information into a register is known as loading the register. When all bits of the register are loaded simultaneously with a common clock pulse transition, this is called parallel loading. For example, applying a clock transition to the inputs of a 4-bit register will load all four inputs in parallel. To keep the register content unchanged, the clock signal must be inhibited.

In most digital systems, a master clock generator provides a continuous train of clock pulses to all flip-flops and registers in the system. The master clock acts like a pump that supplies a constant beat to all system parts. A separate control signal decides which specific clock pulse affects a particular register.

A 4-bit register with a load control input, directed through gates into the D inputs, is often used. The clock inputs receive pulses continuously. The buffer gate in the clock input reduces power requirements. The D input determines the next state of the output with each clock pulse. To leave the output unchanged, the D input must equal the present value of the output.

The load input controls whether the next pulse will accept new information or leave the register information intact. Information transfer from the inputs into the register occurs simultaneously for all four bits during a single pulse transition.

Shift Registers

A shift register can shift its binary information in one or both directions. It consists of a chain of flip-flops in cascade, with the output of one flip-flop connected to the input of the next. All flip-flops receive common clock pulses that initiate the shift from one stage to the next.

Simple Shift Register

The simplest shift register uses only flip-flops. The output of one flip-flop connects to the D input of the next. The clock is common to all flip-flops. The serial input determines the leftmost position during the shift, while the serial output is taken from the rightmost flip-flop.

To control shifts selectively, the clock can be inhibited from the register input when shifts are not desired. Alternatively, extra circuits can control the shift operation through the D inputs of the flip-flops instead of the clock input.

Bidirectional Shift Register with Parallel Load

A bidirectional shift register can shift in both directions. It may include input and output terminals for parallel transfer. The most general shift register configuration includes:

1. An input for clock pulses to synchronize all operations.
2. A shift-right operation with a serial input line.
3. A shift-left operation with a serial input line.
4. A parallel load operation with n input lines.
5. n parallel output lines.
6. A control state that maintains register information unchanged despite continuous clock pulses.

Example: 4-bit Bidirectional Shift Register

Consider a 4-bit bidirectional shift register with parallel load, consisting of D flip-flops and a 4x1 multiplexer for each stage. Two selection inputs ($S_1$ and $S_0$) determine the multiplexer data input for the D flip-flop. The register operates as follows based on the selection inputs:

• $S_1S_0 = 00$: The output of each flip-flop is fed back to its input, causing no change in state.
• $S_1S_0 = 01$: The register performs a shift-right operation. The serial input data enters the leftmost flip-flop ($A_0$), and the content of each flip-flop is shifted to the right.
• $S_1S_0 = 10$: The register performs a shift-left operation. The other serial input data enters the rightmost flip-flop, and the content of each flip-flop is shifted to the left.
• $S_1S_0 = 11$: Parallel load operation occurs, transferring binary information from inputs into corresponding flip-flops.

Shift registers are often used to interlace digital systems situated remotely from each other. For example, transmitting an n-bit quantity between two distant points might be expensive if done in parallel. It is more economical to use a single line for serial transmission. The transmitter loads the n-bit data in parallel into a shift register and sends the data serially. The receiver collects the data serially into a shift register, then transfers it in parallel. This method effectively converts parallel data to serial at the transmitter and serial data to parallel at the receiver.