Bus and Memory Transfers

Common Bus System

A typical digital computer comprises many registers, and efficient paths must be provided to transfer information between them. Using separate lines for each register-to-register connection would require an excessive number of wires. Instead, a common bus system provides a more efficient means of transferring information between registers in a multiple-register configuration.

A bus structure consists of a set of common lines, one for each bit of a register, through which binary information is transferred one at a time. Control signals determine which register is selected by the bus during each particular register transfer.

Construction Using Multiplexers

One way to construct a common bus system is with multiplexers. The multiplexers select the source register, whose binary information is then placed on the bus. Consider a system with four registers, each containing four bits. The bus consists of four 4x1 multiplexers, each having four data inputs (0 through 3) and two selection inputs ($S_1$ and $S_0$). To avoid complicating diagrams with 16 crossing lines, labels are used to show connections from register outputs to multiplexer inputs. For example, the output bit 1 of register A is connected to input 0 of MUX 1, as indicated by the label $A_1$.

Each bit position in the registers is connected to the data inputs of one multiplexer to form a line of the bus. Thus, MUX 0 multiplexes the four 0 bits of the registers, MUX 1 multiplexes the four 1 bits, and so on. The selection lines $S_1$ and $S_0$ are connected to the selection inputs of all four multiplexers. Depending on the combination of $S_1$ and $S_0$, the four bits from one register are transferred to the four-line common bus.

For instance, if $S_1S_0 = 00$, the 0 data inputs of all four multiplexers are selected, applying the contents of register A to the bus. If $S_1S_0 = 01$, register B is selected, and so forth. The function table below shows the register selected by the bus for each combination of selection lines:

In general, a bus system will multiplex $k$ registers of $n$ bits each to produce an $n$-line common bus. The number of multiplexers required is equal to $n$, the number of bits in each register, and each multiplexer must have $k$ data input lines. For example, a common bus for eight registers of 16 bits each requires 16 multiplexers, each with eight data input lines and three selection lines to multiplex one significant bit from the eight registers.

Transfer from Bus to Registers

Information transfer from a bus to a destination register is accomplished by connecting the bus lines to the inputs of all destination registers and activating the load control of the selected register. Symbolically, bus transfers are denoted as follows:

This indicates that the content of register $C$ is placed on the bus, and then the content of the bus is loaded into register $R1$ by activating its load control input. Alternatively, if the existence of the bus is implied, the transfer can be written directly as:

From this, the designer understands which control signals must be activated to perform the transfer via the bus.

Three-State Bus Buffers

A bus system can also be constructed using three-state gates instead of multiplexers. A three-state gate is a digital circuit that has three states: logic 1, logic 0, and high-impedance. The high-impedance state acts as an open circuit, effectively disconnecting the output. This feature allows multiple three-state gate outputs to connect to a common bus line without causing loading effects.

Construction Using Three-State Buffers

To construct a bus system with three-state buffers, each buffer's output is connected to a single bus line. The control inputs of the buffers determine which input will communicate with the bus line. Only one buffer may be active at any time, while the others are in a high-impedance state.

A decoder can ensure that only one buffer is active at a time. When the decoder's enable input is inactive, all its outputs are 0, placing the bus in a high-impedance state. When the enable input is active, one buffer is selected based on the decoder's select inputs.

For a common bus with four registers of $n$ bits each using three-state buffers, $n$ circuits with four buffers each are needed. Each group of four buffers receives one significant bit from the four registers. A single decoder selects between the four registers.

Memory Transfer

The operation of a memory unit involves reading and writing information. A read operation transfers data from a memory word to an external register, while a write operation stores new data into a memory word. A memory word is symbolized by the letter $M$, and its address is specified in square brackets following $M$.

Read Operation

The read operation transfers information from a memory word to a data register (DR). Assuming the address register (AR) contains the address of the memory word, the read operation is represented as:

This causes the data from the memory word at the address specified by $AR$ to be transferred into $DR$.

Write Operation

The write operation transfers data from a data register to a memory word. Assuming the data is in register $R1$ and the address is in $AR$, the write operation can be represented as:

This causes the data in $R1$ to be stored into the memory word at the address specified by $AR$.

Arithmetic Microoperations

Arithmetic microoperations perform arithmetic functions on the data stored in registers. Common arithmetic microoperations include addition, subtraction, increment, and decrement. A 4-bit binary adder is shown below.

Addition and Subtraction

To implement addition, we use registers that hold data and a digital component, such as a full-adder, that performs the arithmetic addition. A binary adder generates the sum of two binary numbers of any length.

The subtraction operation is conveniently done using complements. Subtracting $B$ from $A$ can be achieved by taking the 2's complement of $B$ and adding it to $A$. The 2's complement is obtained by taking the 1's complement and adding one to the least significant bit. This can be implemented using exclusive-OR gates with full-adders to form a binary adder-subtractor.

Binary Incrementer

The increment microoperation adds one to the value in a register. This can be implemented with a binary counter or with a combinational circuit using half-adders connected in cascade. For example, a 4-bit binary incrementer adds one to a 4-bit number and generates the incremented output.

Arithmetic Circuit

A composite arithmetic circuit can implement various arithmetic microoperations using a parallel adder. By controlling the data inputs to the adder, different operations can be performed. A 4-bit arithmetic circuit with multiplexers and full-adders can perform operations such as add, subtract, increment, and decrement by selecting appropriate inputs.

The function table for the arithmetic circuit is as follows:

The arithmetic microoperations are implemented by controlling the data inputs and the carry-in to a binary adder, enabling the execution of various operations such as addition, subtraction, increment, and decrement.